Pipelined converters have become the predominant architecture for ADCs with resolutions of 8-14 bits and conversion rates of 10-200MS/s. Figure 1 shows a conceptual block diagram of this converter topology. Several converter stages are cascaded and process the analog input sequentially, analogous to flip-flops propagating a bit stream in a digital shift register.

Each stage performs a sample and hold operation and a coarse A/D conversion. The local quantization result is converted back into analog form and used to compute the error in the coarse digital approximation D. The locally computed and amplified quantization error, often called the residuum (Vres), propagates through subsequent stages which resolve further less significant digital information of the initial input sample. After the signal has passed through all stages, the sub quantization results are combined to yield the final digital output word.

The main advantage of this architecture is that due to stage pipelining, its throughput rate is set by the time needed to perform a single sub-A/D and D/A conversion. The fact that the signal needs to propagate though all stages until the final conversion result becomes available results only in conversion latency, which is tolerable in many signal processing applications. Also shown in Figure 1 is an ideal pipeline stage transfer function, Vres as a function of stage input voltage Vin, for the simple case of a 1-bit subconversion. In this example, the residuum segments have a slope of 2. More generally, it can be shown that in a stage that resolves R bits, a gain factor of 2R is needed.

## Open-loop pipeline stages

Recently, the benefits of using open-loop structures in high-speed pipelined ADCs have been recognized and demonstrated. Many 8-bit ADCs use open-loop, current mode residue amplification to achieve excellent power efficiency at high conversion speeds. Here, we propose a voltage mode topology in conjunction with digital calibration to extend the applicability of open-loop structures to resolutions of greater 10 bits. Figure 3 shows a conceptual schematic diagram of the proposed stage implementation.

Except for the charge redistribution phase, the operation of this circuit is similar to the conventional topology described above. Unlike in the closed loop implementation, the residual charge packet on the capacitive array is not redistributed onto a feedback capacitor, but remains in place to produce a small voltage at node Vx. This residuum is fed into a resistively loaded transconductance stage to produce the desired full-swing residue voltage Vres. Since the high gain requirement in the transconductor is now dropped, a simple differential pair can be used to replace the complex amplifier in

Figure 2 . This modification results in significant power savings and also mitigates technology-scaling issues. These advantages, however, come at the price of several new nonidealities in the stage transfer function.

## Open-Loop Stage Analysis

With sufficient loop gain in the conventional implementation of Figure 2, deviations of the stage transfer function from ideality are mostly due to capacitor mismatch and offset errors in the coarse sub-ADC. With the introduction of the simplified, open-loop amplifier of Figure 3, several additional error sources must be considered. Figure 4 depicts an appropriate model for further analysis.

Here, the capacitor array is replaced with its Thévenin equivalent, consisting of the total array capacitance Cstot and an equivalent voltage source Veq that represents the local stage residuum before amplification.

Ideally, the transfer function from Veq to the output Vres should be linear with a precise gain of 2R, where R is the effective stage resolution. In the circuit of Figure 4, the transfer function is neither linear nor precisely defined. The linear gain term from source to output is set by the amount of parasitic capacitive attenuation at node Vx and the Gm·R product, which typically cannot be accurately controlled.

Furthermore, the amplification is nonlinear, primarily due to three effects:

- voltage dependence of the capacitor Cx, which represents the transconductor input capacitance and parasitic junctions;
- nonlinearity in the resistive load;
- nonlinearity in the V-I relationship of the transconductor.

With respect to the tolerable errors in a pipelined ADC, none of the above nonlinearities may be negligible. However, for a practical and optimized implementation, it is reasonable to assume that the differential pair dominates the overall cascade nonlinearity that links Veq and Vres. In the analysis, we therefore should focus on this particular error component, noting that some additional, but non-dominant distortion is actually due to other non-idealities.

## Example: MCP37210-200

The MCP37210-200 is a **12-bit** pipelined A/D converter with a maximum sampling rate of **200 Msps**. The high accuracy of over **67 dB Signal-to-Noise Ratio (SNR)** and **96 dB Spurious Free Dynamic Range (SFDR)** enable high precision measurements of fast input signals.

The device operates at very low power consumption of **338 mW at 200 Msps** including LVDS digital I/O. Lower power saving modes are available at 80 mW for Standby and 33 mW for Shutdown.

The MCP37210-200 includes many digital processing features that simplify system design, cost and power usage. These include integrated decimation filters for improved SNR, a noise-shaping requantizer for noise improvement over a designated bandwidth, and phase, offset and gain adjustment. Data is available through the serial DDR LVDS or parallel CMOS interface and configured via SPI. The device is available in the TFBGA-121 and VTLA-124 packages.

Go to MCP37210-200 documentation

Reference: *DIGITALLY ASSISTED PIPELINE ADCs, Boris Murmann & Bernhard E. Boser, KLUWER ACADEMIC PUBLISHERS*